This invention relates generally to semiconductor devices and methods for fabricating MOSFET devices having high-k gate dielectric stacks.
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a metal or polysilicon gate contact is energized to create an electric field within a semiconductor channel, by which current is allowed to conduct between a source region and a drain region. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel region in a semiconductor substrate. A gate dielectric is formed over the channel region, and a gate contact (e.g., metal or doped polysilicon) is formed over the gate dielectric. The gate dielectric is an insulator material, which prevents large currents from flowing from the gate into the channel when a voltage is applied to the gate contact, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner.
FIG. 1a illustrates a conventional semiconductor device 2 with both PMOS and NMOS transistor devices 4 and 6, respectively. The device 2 is fabricated using conventional complimentary MOS (CMOS) processing techniques in a semiconductor substrate 8, in which isolation structures (e.g., SiO2 field oxide (FOX) or shallow trench isolation (STI) structures) 10 are formed to separate and provide electrical isolation of the individual devices 4 and 6 from other devices and from one another. The substrate 8 is lightly doped p-type silicon with an N-well 12 formed therein under the PMOS transistor 4. The PMOS device 4 includes two laterally spaced P-doped source/drain regions 14a and 14b with a channel region 16 located therebetween. A gate is formed over the channel region 16 comprising an insulative gate dielectric layer 20, such as silicon dioxide (SiO2) overlying the channel 16 and a conductive polysilicon gate contact structure 22 formed over the gate dielectric layer 20.
The NMOS device 6 includes two laterally spaced N-doped source/drain regions 24a and 24b with a channel region 26 located therebetween. A gate is formed over the channel region 26 comprising an insulative gate dielectric layer 30, such as silicon dioxide (SiO2) overlying the channel 26 and a conductive polysilicon gate contact structure 32 formed over the gate dielectric layer 30. Typical CMOS production processing has thusfar not adopted high-k gate dielectric layers, although such layers are being studied. Instead, the gate dielectric layer 30 of FIG. 1a is typically formed through thermal oxidation of the silicon substrate 8 to form the layer 30 of SiO2.
In operation, the resistivity of the channel 26 may be controlled by the voltage applied to the gate contact 32, by which changing the gate voltage changes the amount of current through channel 26. The gate contact 32 and the channel 26 are separated by the gate dielectric stack 30, which is an insulator. Thus, little or no current flows between the gate contact 32 and the channel 26, although xe2x80x9ctunnelingxe2x80x9d current is observed with thin dielectrics. However, the gate dielectric allows the gate voltage to induce an electric field in channel 26, by which the channel resistance can be controlled by the applied gate voltage.
Field-effect transistors such as transistors 4 and 6 of FIG. 1a are physically very small in many cases, whereby many such devices may be formed on a single-crystal silicon substrate or chip and interconnected in an integrated circuit. In the field of semiconductor device technology, there is a continuing trend toward higher device densities, and hence smaller and smaller device dimensions. Generally, device density is improved by scaling or decreasing the size of the transistors and other electrical components. At the same time, however, MOSFET devices produce an output signal proportional to the ratio of the width over the length of the channel, where the channel length is the physical distance between the source/drain regions (e.g., between regions 24a and 24b in the device 6) and the width runs perpendicular to the length (e.g., perpendicular to the page in FIG. 1a). Thus, scaling the MOSFET device 6 to make the width narrower may reduce the device output. Previously, this characteristic has been accommodated by decreasing the thickness of gate dielectric 30, thus bringing the gate contact 32 closer to the channel 26 for the device 6 of FIG. 1a. Making the gate dielectric layer 30 smaller, however, has other effects, which may lead to performance tradeoffs.
In particular, there are limitations in the use of silicon dioxide in the formation of thinner gate dielectric layers. For instance, extremely thin SiO2 layers allow for large gate tunneling leakage currents due to direct tunneling through the oxide. This problem is exacerbated by limitations in the ability to deposit such thin films with uniform thickness. Thus, it has been found that MOSFET operating parameters may change dramatically due to slight variations in gate dielectric thickness. Furthermore, thin gate dielectric layers are known to provide poor diffusion barriers to impurities. Thus, for example, extremely thin SiO2 gate dielectric layers suffer from high boron penetration into the underlying channel region during implantation of source/drain regions outlying the channel region. Consequently, recent efforts at MOSFET device scaling have focused on alternative dielectric materials which can be formed in a thicker layer than scaled silicon dioxide layers and yet still produce the same field effect performance. These materials are often referred to as high-k materials because their dielectric constants are greater than that of SiO2. The relative performance of such high-k materials is often expressed as equivalent oxide thickness (EOT), because the alternative material layer may be thicker, while providing the equivalent electrical effect of a much thinner layer of SiO2.
Referring to FIG. 1b, one proposed alternative structure for applying high-k gate dielectric materials in a gate dielectric layer 30xe2x80x2 is illustrated in a MOSFET device 6xe2x80x2 including a layer of dielectric (e.g., oxide) material 30a deposited using standard deposition processing techniques, such as chemical vapor deposition (CVD) or sputtering processes. A conductive polysilicon gate contact structure 32xe2x80x2 is then formed over the gate dielectric layer 30a. However, an undesirable (e.g., low-k) interfacial layer 30b is formed between the substrate 8 and the deposited oxide 30a. The interfacial layer 30b is not directly deposited, but instead is the result of oxidation of the substrate material 8 during deposition of the oxide layer 30a. 
Referring also to FIG. 2, a sectional TEM view is provided of a portion of an actual high-k gate structure 50 overlying a semiconductor substrate 52. In the gate structure 50, an interfacial layer 56 is formed during sputtering deposition of a hafnium silicon oxide dielectric layer 54 with O2 employed in the deposition process. The deposited gate dielectric layer 54 is illustrated underlying a subsequently deposited polysilicon gate contact layer 58. During deposition of the oxide material layer 54, the low-k interfacial layer 56 is formed between the substrate 52 and the gate dielectric layer 54, due to deposition process related oxidation of the substrate 52. Thus, from FIG. 2 it is seen that the relative thicknesses 54a and 56a of the gate dielectric and the interfacial layers, respectively, can be quite significant in practice (e.g., about 27 xc3x85 and 26 xc3x85, respectively).
At the same time, however, the alternative materials explored thusfar are typically comprised of oxygen components, and are often deposited using oxidizing deposition processes. As a result, these substitute or alternative gate dielectric materials also suffer from the formation of the interfacial layer (e.g., layer 30b in FIG. 1b) during sputtering or CVD type deposition. For example, where high-k metal oxides are deposited, such as tantalum pentoxide, titanium dioxide, and barium strontium titanate, hafnium dioxide, aluminum oxide, hafnium silicate, the oxygen ambient or oxygen-containing precursor in the deposition process tends to also oxidize the silicon substrate, producing an interfacial oxide layer (e.g., layer 30b) at the interface between the substrate and the gate dielectric. The presence of this interfacial oxide layer increases the effective oxide thickness, reducing the effectiveness of the alternative gate dielectric approach. Thus, the interfacial oxide layer 30b limits the effectiveness of such alternative dielectric field effect devices.
Thus, in attempting to provide an oxide thickness equivalent to that of a very thin SiO2 layer, sputtered and CVD deposited high-k oxide gate materials suffer from the formation of low-k interfacial layers. The low-k interfacial layer, in turn, decreases the overall capacitance of the dielectric stack (e.g., gate dielectric stack 30) due to series capacitor effects. Consequently, there remains a need for improved scaling techniques by which high-k dielectric materials can be employed in forming gate dielectric layers while mitigating or avoiding the adverse effects of low-k interfacial layers.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to methods for forming gate dielectric structures for MOSFET devices, wherein high-k dielectric or other gate oxide materials can be deposited while avoiding or mitigating the formation of uncontrolled low-k interfacial layers. Thus, the invention provides significant advances in the further scaling of MOSFET devices, allowing flexibility in the selection and employment of new and improved high-k dielectric materials.
One aspect of the invention involves using bilayer gate dielectric stack structures, where a first layer in the stack is a nitride layer (other than silicon nitride (SiN) or nitrided silicon) deposited over the substrate. Some examples of nitrides which may be employed include hafnium silicon nitride, zirconium silicon nitride, hafnium nitride, and zirconium nitride, although other compositions are contemplated as falling within the scope of the invention. As used hereinafter, the term nitride layer is used to refer to such materials and others, apart from silicon nitride (SiN) and nitrided silicon. An oxide layer is then deposited over the nitride layer, which can be of any high-k material, such as tantalum pentoxide, titanium dioxide, barium strontium titanate, hafnium oxide, zirconium oxide, aluminum oxide, hafnium silicon oxide, zirconium silicon oxide, hafnium aluminum oxide, zirconium aluminum oxide, strontium titanium oxide, or others. The inventors have found that this technique can be advantageously employed to eliminate or reduce the formation of a low-k interfacial oxide layer due to the absence or reduced presence of reactive oxygen during the initial nitride layer deposition process. Thus, the invention provides for gate dielectric stack formation without low-k interfacial layer formation found in conventional dielectric stacks.
Another aspect of the invention provides for controlled oxidation of the nitride layer, either during deposition of the overlying oxide layer, or in a separate thermal annealing process. For example, the ambient deposition environment used in depositing the oxide layer may be employed to transform the initial nitride layer (either partially or wholly) to oxide in a controlled fashion, while at the same time, the nitride layer protects the underlying silicon substrate from oxidation. In this manner, the nitride layer can serve as a sacrificial layer, and the relative thicknesses of the nitride and oxide layers can be tailored to either fully oxidize the initial nitride layer, or to leave a desired portion thereof unoxidized.
Alternatively or in combination, the nitride layer thickness may be adjusted relative to that of the oxide layer so as to allow a reduced oxidation of the underlying silicon substrate relative to the conventional case where no nitride layer is present. This technique may be advantageously employed to ensure that the initial layers in the stack include a controllable amount of silicon dioxide, to mitigate or avoid mobility degradations associated with metal at the interface. Another aspect provides for a controlled post-deposition oxidation, such as through a thermal annealing process, to either fully or partially oxidize the nitride layer, and/or to form a controllable amount of SiO2 at the bottom of the gate dielectric stack. The oxide deposition processing and the post-deposition oxidation processing may be employed individually or in combination, in order to controllably oxidize a desired amount of the nitride layer. The invention thus provides significant processing advantages in the manufacture and design of scaled MOSFET devices, which can be employed in association with various deposition processes, such as an atomic layer deposition process (ALD), CVD, and sputtering deposition.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.